Publications

Journals, Book chapters

1. A. Sateesan, J. Biesmans, T. Claesen, J. Vliegen, and N. Mentens. "Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware" Microprocessors and Microsystems (2023).
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2. A. Sateesan, J. Vliegen, J. Daemen and N. Mentens. "Hardware-oriented Optimization of Bloom Filter Algorithms and Architectures for Ultra-high-speed Lookups in Network Applications" Microprocessors and Microsystems (2022).
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3. Sateesan, Arish, Sharad Sinha, K. G. Smitha, and A. P. Vinod. "A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs." Neural Processing Letters, Vol 53, 2331-2377, 2021. DOI: doi.org/10.1007/s11063-021-10458-1
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4. Arish S, R.K.Sharma, “Run-time Reconfigurable Multi-precision Floating Point Matrix Multiplier Intellectual Property Core on FPGA”, International Journal of Circuits, Systems and Signal Processing, Vol 36, 998-1026, 2017. DOI: doi.org/10.1007/s00034-016-0335-2
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Conference Proceedings

1. Simon Scherrer, Jo Vliegen, Arish Sateesan, Hsu-ChunHsiao, Nele Mentens, and Adrian Perrig. "ALBUS: a Probabilistic Monitoring Algorithm to Counter Burst-Flood Attacks." In Proceedings of the 42th International Symposium on Reliable Distributed Systems(SRDS), 2023.
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2. Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens. "Evolving Non-cryptographic Hash Functions Using Genetic Programming for High-speed Lookups in Network Security Applications" In International Conference on the Applications of Evolutionary Computation (EvoApplications), 2023.
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3. Arish Sateesan, Jo Vliegen, Nele Mentens. "An Analysis of the Hardware-Friendliness of AMQ Data Structures for Network Security" In International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE), 2022.
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4. Laurens Le Jeune, Arish Sateesan, Md Masoom Rabbani, Toon Goedemé, Jo Vliegen, Nele Mentens. "SoK - Network Intrusion Detection on FPGA." In International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE), 2021.
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5. Simon Scherrer, Che-Yu Wu, Yu-Hsi Chiang, Benjamin Rothenberger, Daniele E Asoni, Arish Sateesan, Jo Vliegen, Nele Mentens, Hsu-ChunHsiao, and Adrian Perrig. "Low-rate overuse flow tracer (loft): An efficient and scalable algorithm for detecting overuse flows." In Proceedings of the 40th International Symposium on Reliable Distributed Systems(SRDS), 2021.
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6. Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, and Nele Mentens. "Speed Records in Network Flow Measurement on FPGA." In 31st International Conference on Field-Programmable Logic (FPL), 2021.
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7. Thomas Claesen, Arish Sateesan, Jo Vliegen, and Nele Mentens. "Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA." In 24th international conference on Digital System Design (DSD), 2021.
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8. Sateesan, Arish, Sharad Sinha, and K. G. Smitha. "DASH: Design Automation for Synthesis and Hardware Generation for CNN." In 2020 International Conference on Field-Programmable Technology (ICFPT), pp. 72-75. IEEE, 2020.
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9. A. Sateesan, J. Vliegen, J. Daemen and N. Mentens, "Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications," 2020 23rd Euromicro Conference on Digital System Design (DSD), Kranj, Slovenia, 2020, pp. 262-269, doi: 10.1109/DSD51259.2020.00050
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10. Arish S, Sharad Sinha, Smith K G, “Optimization of Convolutional Neural Networks on Resource Constrained Devices”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, DOI: doi.org/10.1109/isvlsi.2019.00013
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11. Arish S, R.K.Sharma, “Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications”, IEEE International Conference on Signal Processing and Integrated Networks(SPIN), pp. 902 - 907, 2015, DOI: doi.org/10.1109/spin.2015.7095315
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12. Arish S, R.K.Sharma, “An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm”, IEEE International Conference on Signal Processing and Communication(ICSC), pp. 303-308, 2015, DOI: doi.org/10.1109/icspcom.2015.7150666
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13. Arish S, R.K.Sharma, “An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm”, IEEE Global Conference on Communication Technologies (GCCT), pp. 192-196, 2015, DOI: doi.org/10.1109/gcct.2015.7342650
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