Research
Ongoing
FPGA design for Network Security
This work concentrates on the acceleration of large flow detection algorithms on FPGAs. An algorithm-architecture co-design approach is followed to develop novel algorithms and implementations for detecting data flows that only exceed the allowed bandwidth to a limited extent. Probabilistic data structures and approximate computing are employed to develop hardware-efficient architectures for large flow detection targeting Terabit Ethernet. The goal is to integrate the configurable hardware in network devices and demonstrate efficient and effective protection against large flow network attacks in high-speed networks.
Past
Optimization of Machine Learning Algorithms on Resource-Constrained devices
The main aim of this project was to Optimize deep learning algorithms, especially vision-based neural networks, both on algorithmic and hardware level and develop an automated tool for hardware-efficient implementation on FPGAs using Python and Verilog.